Generally, conductive traces made of metals such as copper are formed on the surface of a conventional semiconductor package substrate. Connecting pads extend from the conductive traces for providing a signal transmission means. Typically, in order to electrically connect conductive elements such as gold wires, solder bumps, or solder balls to a chip or a printed circuit board (PCB), the exposed surface of the electrical connecting pads must be plated with a metal layer such as a Nickel/Gold (Ni/Au) or Nickel/Silver (Ni/Ag) layer. Conventional electrical connecting pads include bump pads for providing electrical connection between a flip-chip package substrate and the chip, presolder pads, and fingers for a wire bonding package to electrically connect the chip, or ball pads for providing electrical connection between the substrate and other PCBs. In addition, with the provision of a Ni/Au metal layer formed on the electrical connecting pads, it is possible to prevent oxidation of the connecting pads as well as to improve the solder joint reliability between conductive elements and the electrical connecting pads.
There are several conventional methods for plating such as the chemical method, electroplating, sputtering, and plasma deposition. However the chemical method has the drawback of low bonding reliability resulting from skip plating or black pads, and sputtering or plasma deposition are both costly. Thus, the most common method of forming the metal layer is either electroplating or the electroless plating method.
As shown in FIG. 8, plating a Ni/Au metal layer on a semiconductor package substrate is typically achieved by forming several electrical connecting pads 24 on a semi-completed substrate 2 in which upper and lower conductive trace layers 21, 22 and several through holes 23 are formed via development and etching processes. Further, the outer surface of the substrate 2 is covered by a solder mask 25.
In order to plate a Ni/Au metal layer on the electrical connecting pad 24, it is necessary to dispose a plurality of plating lines 27 on the conductive traces to supply electric current for electroplating the Ni/Au layer 26 on the electrical connecting pad 24. As such, the substrate surface is largely occupied by the plating lines, and, moreover, the plating lines may result in radiating electromagnetic noise when the package operates at high frequency. Although noise can be reduced by using an etchback method to sever the connections for the plating lines 27, the terminal parts of the plating lines still exist in the form of an undesirable maze with a large number of disconnected terminals. Thus, the problem of insufficient circuit layout area and noise still remains.
In order to solve the above-mentioned electroplating problem, a common gold pattern plating (GPP) has been proposed. As shown in FIG. 9A, the manufacturing process starts with the formation of a conductive layer 31 on both the top and bottom surfaces of the substrate 3 which are electrically connected to each other via the provision of a plurality of plating through holes (PTH) or blind vias (both not shown).
Following that, as shown in FIG. 9B, the conductive layers 31 of the substrate are covered by photoresist layers 32 having openings to allow regions of the conductive layer 31 where the conductive circuits are formed later thereon to be exposed. And a Ni/Au layer 33 is formed on the uncovered regions of conductive layers 31 by electroplating via the conductive layer 31 which acts as a conductive path for electric current.
Further, as shown in FIG. 9C, the photoresist layer 32 is then removed, and then, by using etching technology, the conductive layer 31 under the Ni/Au metal layer 33 is patterned to form a patterned circuit 310 covered by the Ni/Au metal layer 33, as shown in FIG. 9D.
Gold pattern plating technology utilizes a conductive layer instead of plating lines to allow electric current to pass through; however, the overall cost of materials is very high as the entire circuit layer (including electrical connecting pads and all conductive circuits) is covered with the Ni/Au metal layer. Moreover, during the latter procedure of circuit patterning, because the circuit layer is entirely covered with the Ni/Au layer and the material property of the solder mask greatly differs from that of the Ni/Au metal, stable adhesion between the two is very difficult to achieve. Thus, in order to solve the above-mentioned problems, a non-plating line (NPL) technology has been proposed to form the Ni/Au metal layer on the electrical connecting pads.
The non-plating line (NPL) technology provides a method of forming an electroplated metal layer on the electrical connecting pad without the need of plating lines; however, it has some drawbacks when applied to a semiconductor package substrate with a high density of circuit layout and fine pitch. Referring to FIG. 10, because the pitch between any two electrical connecting pads 42 is reduced, it is common for the two openings 411 of the conductive films 41 from adjacent connecting pads to partly overlap. In the case of connecting pads being arranged in a ring array where the region on the substrate 4 is circularly surrounded by isolated pads, the partly overlapping openings 411 of the conductive films 41 will be connected with each other, which leads to open-circuit regions incapable of connecting with external electric current, and thus ultimately preventing electroplating of the isolated pads 42. Moreover, when NPL is applied in a substrate design with a high density of circuit layout and fine pitch, the periphery of the isolated pads will have insufficient area for disposing several plating lines outwardly onto the conductive film 41. Thus, even though plating lines could be disposed for providing electrical current, electroplating is still not possible on the isolated pads 42 in the open-circuit region if there is no room to dispose the plating lines.
Therefore, manufacturers are now trying to develop a method of manufacturing a semiconductor package substrate with an electroplated metal layer formed on isolated pads using a simplified manufacturing procedure with reduced cost that does not posses the reliability concerns of the conventional electroplating method and avoids the drawback that the electroplated metal layer cannot be formed on isolated pads within a ring array area.